1. Field of the Invention
The present invention relates to a chemical mechanical polishing (CMP) method and composition having applicability to the manufacture of ferroelectric random access memory capacitors, in which a stop layer is employed over the capacitor recess dielectric material to achieve the required planarization of the microelectronic device structure. It is also applicable to the fabrication of other integrated circuit structures, such as capacitor, resistor and inductor structures, which in utilizing multilayer geometries benefit from the inherently planarizing character of CMP.
2. Description of the Related Art
There is currently a major effort in semiconductor companies, worldwide, to commercialize high dielectric constant and ferroelectric thin films in advanced DRAMs and ferroelectric random access memories (FeRAMs), respectively. These material s include BaSrTiO3 (BST) for DRAMs and PbZrTiO3 (PZT) and SrBi2Ta2O9 (SBT) for FeRAMs.
It is well known that these materials require electrodes made from noble metals or noble metal alloys such as Pt, Ir, IrO2, Ptxe2x80x94Ru, etc., and sub-micron patterning of both the noble metals and the ferroelectric films is very difficult because of the absence of volatile products for the elemental constituents. State-of-the-art dry etching processes for Pt and Ir are known to have fundamental difficulties due to the predominantly physical (not chemical) mechanism for material removal, resulting in formation of unwanted structures (sometimes called xe2x80x9cearsxe2x80x9d) at the edges of the electrodes.
Besides the difficulties in patterning sub-micron capacitors of this type, for high memory density it is also important to fabricate the capacitors directly over a conductive plug to contact transistors in order to reduce the area of the memory cell. This geometry (capacitor over plug) is also known as a stack capacitor configuration. For the conventionally employed materials, e.g., polysilicon or tungsten for the plug, a barrier layer is needed to prevent oxidation of the plug and diffusion of the plug material (p-Si or W) through the noble metal bottom electrode. To overcome such problems, it is desirable to use geometric means to protect the plug/barrier/electrode interfaces from exposure to oxidation.
At present, physical vapor deposition methods and stack capacitor configurations are predominantly used for the fabrication of DRAM and FeRAM microelectronic device structures.
An alternative to the stack capacitor is a trench capacitor, which utilizes an enhanced surface area capacitor on the walls of a trench that is etched directly into doped silicon. In such trench capacitors, the bottom electrode contact is not to a conductive plug (p-Si or W) but to the conductive substrate itself, though the requirements for the barrier are similar to the stack configuration. In trench capacitor architecture, the memory cell""s transistors are formed on the surface of wafer adjacent to the top of the trench capacitor.
Ferroelectric capacitors planarized using chemical mechanical polishing are also more versatile for monolithic integration of ferroelectric memory or dynamic random access memory (DRAM) with logic IC (xe2x80x9cembedded memoryxe2x80x9d). The 4-6 levels of metal needed for logic ICs place additional demands on the planarity of the underlying structures. Surface flatness is required in high resolution microlithography in order to stay within the aligner""s specified depth of focus.
A variety of semiconductor integrated circuits utilize passive (and in some cases active) filtering techniques that use resistors, capacitors, inductors. There is an accelerating trend toward the incorporation of multiple circuit functions in a single IC, whereas in the past different IC""s were fabricated and connected externally on a circuit board, or by another packaging scheme.
Given the economic and performance advantages of monolithic integration of these functions, it is highly desirable to fabricate compact RLC elements directly on the chip during fabrication of the other parts of the IC. It is essential to minimize the number of processing steps as much as possible, and to achieve the highest possible yield for IC devices that are manufactured.
By way of background to the ensuing description of the present invention, a description is set out below of machines used in conventional CMP process operations, polishing pads and slurry compositions used in chemical mechanical polishing.
Three types of mechanical, rotating actions are typically employed in conventional CMP machines. One such type has a rotating wafer carrier. Another revolves the abrasive pad. A third type spins both the wafer carrier and the abrasive pad simultaneously. The polishing pad is pre-soaked and re-wet continuously with a slurry consisting of various particles suspended in a solution. The polishing particles range in size from 10 to 1000 nanometers. The suspension solution generally comprises a diluted base or acid for polishing oxide and metals, respectively. Upon completion of the planarization, the wafers go through a post-CMP clean process in which the residual slurry, ground oxide/metal particles, and other potential contaminants are removed. Most IC manufacturers use a combination of de-ionized (DI) water rinses and nitrogen air drying to accomplish the post-CMP decontamination.
The two most common uses of CMP are oxide and metal (tungsten) plug planarization. The two most essential components of the CMP process are the slurry and the polishing pad.
The polishing pad, generally a polyurethane-based material, performs two primary functions. The polymeric foam cell walls of the pad aid in removal of the reaction products at the wafer surface and the pores within the pad assist in supplying the slurry to the pad/wafer interface.
Progressively more research efforts have focused on further understanding empirical results of the intimate contact between the pad and the pre-planarization surface. Several peculiarities were originally noticed in the material removal rate (RR) as a function of time, pressure and velocity. Many CMP users noticed that the RR decreased tremendously as high throughput processes were attempted. Research showed that deformation of the pad resulted from the brittle, hard surfaces of the ICs structure. The asperity of the pads, or surface roughness due to the type of material, the density of the xe2x80x9cpockets,xe2x80x9d and abrasive characteristics, was found to decline due to pad layer removal. To alleviate this problem, called xe2x80x9cglazing,xe2x80x9d the pad was conditioned after an experimentally determined amount of time, or wafer runs. The conditioner was composed of a base material (metal), a diamond grit (for cutting), and a grit-bonding material (ni plating). The plating bonded the diamond grit to the base material. The conditioner then effectively removed the top layer of the pad until excess, non-desired particles were removed and the nominal surface characteristics of the pad were restored. Although this approach allowed the same pads to be used for an extended period of time, it also resulted in other complications.
Specifically, the physical bonding of the diamonds and base material ruptured relatively easily during the conditioning process. New methods of bonding as well as enhanced post-conditioning cleaning were pursued. When the diamonds were chemically bonded to the base material, the additional strength made grit detachment less prominent. The new bonding method allowed a factor of ten more wafers to be polished with the same conditioning pads as compared to the number that were able to be polished with the physically grit-bonded pads.
Pad conditioning plays a larger role in planarization of oxide than in planarization of metals since metals tend to have a higher degree of hardness relative to the pad material.
To aid in transporting the slurry to the pad/wafer interface, new pad structures have been designed. Karaki-Doy and other developers have designed polishing pads with continuous grooves in concentric ellipses across the entire pad. This structure was found to deliver the slurry more uniformly to the interface and to augment the amount of debris removal resulting from the CMP process. Most conventional pads consist of xe2x80x9cpocketsxe2x80x9d within the polyurethane which are prone to clogging due to the residual debris discharged during the process. Consequently, Karaki-Doy and other developers placed the grooves in the surface of the pad, and noticed an increased longevity in the conditioning-to-conditioning life of their pads over common types of pads.
Another key element in the amenability of the pad to planarize uniformly is the IC device density and relative layer heights (critical dimensions, CD) of the structure undergoing CMP. CMP tends to polish small, individual features faster than larger, more densely packed features. The oxide removal rate over features 15 microns in width is 60-80% greater than the oxide removal rate over features 60 microns in width. Denser or larger features tend to distribute applied load pressure over a larger area than smaller features. Since the removal rate and pressure are directly related in the direct contact mode, the removal rate decreases since the effective, local pressure decreases. The same principles apply when adjacent layers have a larger height contrast. xe2x80x9cTallerxe2x80x9d features will be planarized quicker, depending on other dimensions and the proximity to other devices.
The foregoing factors add complexity to IC design. If IC manufacturing processes will utilize CMP processing, device dimensions and density are critical and require close scrutiny.
The slurry composition used in CMP comprises abrasive particles suspended in a solvent, or solution. Key factors in the effectiveness of the slurry include particle size and shape, solution pH, weight percent solids of the slurry, the quantity of the slurry delivered, and the reaction time involved.
The purpose of the slurry is simple, yet understanding and modeling all the mechanical and chemical reactions involved is extremely difficult. Essentially, the surface of the material being polished is chemically altered to a softer composition, which is then mechanically removed by the pad and slurry abrasives. Thus, the slurry provides both chemical and mechanical forces in the CMP process. Oxide slurries are relatively new and largely experimental, yet the most common are ferric nitrate with an alumina abrasive and low pH. Some polysilicon and polyimide slurries exist, but are still in the prototype and developmental stages.
To date, most of the research devoted to development of slurry compositions has focused on oxide slurries instead of being directed to metal slurries. Due to the numerous desirable characteristics of tungsten plugs, more attention is being directed to development of selective metal slurries. IBM has developed metal slurries with a tungsten:oxide selectivity of 120:1. This type of planarization is essential to the fabrication of multilevel metals and interlevel connects. Ideally the slurries investigated will produce high removal rates, high selectivity, local uniformity, and good planarity. Since xe2x80x9cperfectxe2x80x9d slurries do not currently exist, inevitable trade-offs have been made in evolving acceptable commercial slurry formulations.
Due to the chemical nature of CMP, various studies have evaluated the influence of differing amounts of slurry introduced at the wafer/pad interface. In the case of oxide slurries, it is believed that the water in the solution reacts with the silicon oxide in the reaction as follows:
(xe2x80x94Sixe2x80x94Oxe2x80x94Sixe2x80x94)+H2Oxe2x86x922(xe2x80x94Sixe2x80x94OH)
Since water has a low diffusivity in silicon oxide, the reaction occurs primarily at the oxide interface under applied load as the abrasive particle moves across the surface. Water diffusion into the oxide results in the breaking of (network-forming) Sixe2x80x94O bonds and the formation of Sixe2x80x94OH. Once all of the Sixe2x80x94O bonds for a given Si atom are hydrated, Si(OH)4 is formed which is soluble in water. Increasing the temperature directly increases the removal rate since the diffusivity of the water rises (specifically the diffusion constant of water in oxide). The most effective pH levels for oxide planarization lie between 9.7 and 11.4.
In the case of metal slurries, the composition is even more critical. Typical slurries incorporate an oxidizer or naturally dissolved oxygen additives to adjust pH levels, and either alumina or colloidal silica abrasives. The oxidizer changes the oxidation state of the metal and consequently produces metal ions. The top oxidized metal layer is more brittle and easily removed with the embedded abrasive particles. If the oxidation potential is too aggressive or the resulting metal compound too soluble, metal corrosion can occur as a result of wet etching. Alloys, galvanic actions, and precise oxidation states (oxidizers) are employed to slow down wet etching and limit the metal corrosion.
Two other key issues relating to the choice of slurry deal with post-CMP clean-up and the introduction of mobile ions to the wafer. Depending on the chemical reaction, oxide slurries can introduce various contaminants to the wafer surface. In terms of particle sizes, KOH-based slurries introduce a larger quantity of 200 nanometer particles than do the NH4OH slurries. That difference translates into a higher probability of scratches (e.g., up to 7 times greater, according to some studies) on the wafer surface when using the KOH slurries. NH4OH slurries also produce a lower concentration of mobile ions than KOH-based slurries, and leave residual films that are easier to remove than the residue from KOH slurries. Environmentally, however, KOH-based slurries afford advantages over NH4OH slurries. No ammonia smell exists when using KOH slurries, KOH slurries are less prone to settle in cleaning tanks and CMP machines, and KOH slurries are more stable in terms of pH, and less temperature dependent than NH4OH slurries.
Although CMP has revolutionized global planarization technology, some significant problems exist. One of the major difficulties is in-situ measuring of the amount of material removed from the wafer surface. Due to inaccurate models, many results of CMP machines are difficult to reproduce and the machines themselves do not exhibit the ability for precise process control. This also leads to difficulty in analyzing feedback, or using in-situ measurements, to make adequate and appropriate process alterations to alleviate process complications. Some CMP slurry analyzers have been designed to measure and detect particle sizes in order to ascertain the abrasive characteristics of slurries more accurately. A few endpoint detection devices, like a stylus profiler, have been developed to monitor removal rates as well. Such efforts will aid in more precisely controlling the entire CMP process, but the analysis techniques and instruments have not been developed to a state of high commercial precision.
Thus, commercial CMP is the focus of substantial development effort, but in essence it continues to comprise the simple unit operations of:
1. reaction of an exposed layer of material (e.g., an insulating inorganic metal oxide and/or noble metal) to produce a wafer-adhered material whose hardness is less than the hardness of the abrasive and whose adhesion to the substrate is less than the original pre-reaction layer; and
2. removal from the substrate of the aforementioned reaction product material using a polishing slurry (abrasive medium).
Illustrative CMP slurry compositions (by principal reaction type) for insulating inorganic metal oxides include the compositions set out below:
A. Acidic or Basic Aqueous Solution:
The art has directed improvements to alkali-containing solutions via aqueous or alcohol solutions of fluorinated silicon oxide particles, specifically the use of H2SiF6.
The abrasive composition comprises Al2O3 and/or SiO2 aqueous solution.
B. Oxidizing Agent (with reduction potential, E0, greater than IV):
The abrasive composition comprises Al2O3 and/or SiO2 aqueous solution.
C. Halogenated or Pseudohalogenated Material (in inert atmosphere):
The abrasive composition comprises Al2O3 and/or SiO2 aqueous solution.
The slurry comprises a non-aqueous halogenated or pseudohalogenated reactant, and preferably includes a liquid organic ligand precursor (e.g., cyclic, acyclic, polycyclic, or aromatic compounds) which upon reaction with the halogenated or pseudohalogenated material form a metal-organic coordination complex which is heterocyclic.
The occurrence of dishing or polishing flaws, particularly with the CMP of soft metals such as Al, Cu or Ag, have been mediated in part by storage/delivery of a polishing agent slurry at reduced temperatures where flocculation or precipitation of the slurry is minimized. In addition, agitation of the polishing media (to inhibit flocculation), as well as temperature and velocity control of the polishing wheel has been shown to improve CMP homogeneity.
The CMP pad wears at an exponential rate during its initial use and then wears linearly with time. Further, the CMP pad does not remove material uniformly as the pad wears. These factors make it difficult to maintain an acceptable removal rate and uniformity in the CMP operation.
The art continues to seek improvements in the CMP process and in the fabrication of ferroelectic devices such as FeRAMs.
Individual spatial dimensions of the top electrode/ferroelectric material/bottom electrode (TE/FE/BE) capacitor in a typical FeRAM are on the order of 100 nm. In order to minimize damage/inhomogeneity during the CMP of this layered structure, the maximum abrasive particle size should be much less than the minimum feature size in the device.
Obstacles facing the commercial use of CMP for ferroelectric-based capacitors with noble metal electrodes include the relatively low chemical reactivity of many noble metals of interest, and the high degree of hardness of various of those metals, especially Ir and Rh. A large degree of mechanical removal of the noble metals and oxide films is necessary to achieve high removal rates, and the CMP process may result in physical or chemical damage to the capacitor layers. Physical damage includes disruption of the microstructure and long range order of the polycrystalline oxide lattice, which is principally responsible for the unique properties of the ferroelectric and high xcex5 oxides. Chemical damage, especially in the ferroelectric layer, may involve removal of specific cations, interdiffusion, de-oxygenation, or introduction of metallic contamination from the polishing media.
One difficulty in the use of CMP for planarization of FeRAM and high permittivity capacitor structures is the difficulty of accurately controlling the removal of oxide materials such as silicon dioxide (SiO2). The ability to control the oxide removal in an accurate and reproducible manner thus would be a significant advance in the art, and would enable more robust CMP processes to be utilized in commercial manufacturing operations.
In contrast to planarization of SiO2 using CMP, planarization of FeRAM or high xcex5 capacitor structures entails CMP definition of the edge of the ferroelectric or high xcex5 layer, where relatively high E-fields are realized in these capacitor applications. Damage to the ferroelectric or metal layers will therefore have large effects on the functionality of the capacitor.
It would therefore be a significant advance in the art, and is one object of the present invention, to provide a method and composition for chemical mechanical polishing that is usefully employed to achieve high rate removals of material while incurring only low levels of physical or chemical damage to the elements of the microelectronic structure undergoing CMP.
Another objective of the invention includes the provision of CMP compositions and methods that are usefully employed in capacitor fabrication, such as stack or trench capacitors including high dielectric or ferroelectric thin films, particularly where metals such as Pt, Ir, Rh, and the like are used for electrode elements in the structure.
Additional objects and advantages of the invention will be more apparent from the ensuing disclosure and appended claims.
The present invention utilizes chemical mechanical polishing for planarization of microelectronic device structures.
The chemical mechanical polishing composition and method of the invention in a preferred aspect are used to delineate ferroelectric or high permittivity capacitors. Such capacitors may be of any suitable type including trench and stack capacitor structures.
The invention facilitates fabrication of microelectronic device capacitor structures in geometries that are only limited by the resolution of the lithography and the conformality of thin film deposition processes. Therefore, the polishing of 0.18 or even 0.12 xcexcm structures is possible without dry etching the noble metals or the thin film capacitor (high dielectric constant material layer or ferroelectric layer). Trench capacitors of this type possess the advantage of having significant contribution of sidewall area, without the need for separate patterning steps for the top and bottom electrode, thus the method of the invention has large economic advantages. Additionally, the approach of the present invention has inherent advantages to protect the plug-barrier-bottom electrode interface from exposure to oxidation.
In one aspect, the present invention relates to a method of forming a microelectronic device structure. Such method includes the steps of forming a capacitor recess dielectric material, depositing a bottom electrode layer, a ferroelectric layer, and a top electrode layer, to form a capacitor precursor structure. This capacitor precursor structure then is planarized by chemical mechanical polishing to yield the ferroelectric capacitor structure, e.g., a stack capacitor or a trench capacitor. One improvement of the invention involves forming the capacitor recess dielectric material to contain a stop layer at the planarization depth, wherein the stop layer has a substantially lower CMP removal rate than the dielectric insulating material and device structure materials under CMP conditions. In this manner, the removal of the dielectric insulating material and device structure materials by CMF under CMP conditions is terminated at the planarization depth by the stop layer.
In addition to the small feature sizes mentioned above, the invention will also find utility in fabrication of larger capacitor structures that do not require increased capacitor area, because of the simplicity of material removal compared to wet or dry etch techniques.
The method of the invention may comprise chemical mechanical polishing of a microelectronic device structure for planarization thereof, wherein:
(I) the CMP medium contains at least one component that is a beneficial dopant, modifier or other additive of the ferroelectric or high xcex5 film being removed in the CMP operation (examples include perovskite nanocrystalline particles, such as those of barium strontium titanate; tantalum oxide, niobium oxide, or other donor dopants compensatory for O vacancies or acceptor impurity defects in the thin film capacitor material when incorporated therein; refractory nitrides and carbides including cations that are beneficial to dielectric and/or ferroelectric properties of thin film capacitor material when incorporated therein, such as tantalum nitride, tantalum carbide, niobium nitride, and niobium carbide; components that have hardness exceeding hardness of chemical byproducts existing at surface of the film being planarized; and reactant components that react with the material at the surface of the film being planarized, such as acids, bases and components that are effective to oxidize the material at the surface of the film being planarized);
(II) metal (electrode material) or dielectric (ferroelectric or high dielectric constant) material is removed either during or after the CMP planarization to create a local recess in the substrate, optionally followed by deposition of an insulating layer thereover, to thereby reduce the susceptibility of the device structure to short-circuiting or high leakage current behavior in use, with such metal removal comprising at least one of the steps of:
inert ion bombardment of the device structure after CMP planarization and before deposition of an interlayer dielectric material (e.g., Pb diffusion barrier layer for PZT device structures, Bi diffusion barrier layer for SBT device structures, and SiO2 diffusion barrier layer for BST device structures); and
isotropic dry etching of the device structure;
(III) physical damage to the device structure crystalline lattice structure is removed by thermal annealing of the device structure after CMP planarization (e.g., by conventional oven processing, or by rapid thermal annealing (RTA), preferably conducting such thermal annealing in the presence of oxygen to facilitate correction of oxygen stoichiometry in the thin film capacitor material and/or other device structure oxide layers;
(IV) noble metal electrode material is removed by a CMP composition comprising component(s) selected from the group consisting of:
silica, alumina, titania, silicon carbide, diamond, ceria, perovskite nanocrystalline particles, dopant materials of the above-described types, and mixtures of the foregoing; and
components reactive with the noble metal electrode material to form solid and/or ionic products having a lower hardness than the noble metal electrode material itself (e.g., nitrides, sulfides, halides, oxides, hydrated oxides, etc. of the noble metal), such reactive components including species such as H2O2, K3Fe(CN)6, K3Fe(C2O4)3, Fe(C2H3O2)3, Fe(NO3)3, Fe2(SO4)3, Fe(OH)3, (NH4)3Fe(CN)6, (NH4)3Fe(C2O4)3, KCl, KBr, KI, FeCl3, FeBr3, FeI3, FeCl2, FeBr2, and FeI2.
In a further aspect of the method of the invention, wherein the metal electrode material is being removed, a high selectivity between metal polishing and oxide polishing is achieved by conducting the CMP operation in accordance with the relationship:
(pressurexc3x97platen speed) less than 300 psi rpm
wherein the pressure is measured in pounds per square inch, and the platen speed of the CMP polishing pad is measured in revolutions per minute.
Still another aspect of the invention relates to a method of fabricating an integrated circuit structure including conductive transmission lines, comprising:
depositing a dielectric material as a component of the structure, and providing pathways therein for the conductive transmission lines,
depositing a transmission-enhancement material in the pathways,
depositing conductor material for the conductive transmission lines on the transmission-enhancement material,
subjecting the structure to chemical mechanical polishing for planarization thereof to define a desired geometry of conductive transmission lines of the conductor material, and
depositing the transmission-enhancement material over the conductive transmission lines of the conductor material, to encapsulate the conductive transmission lines in the transmission-enhancement material,
whereby the transmission-enhancement material enhances the inductance and/or capacitance of the conductive transmission lines, relative to a corresponding integrated circuit structure lacking such transmission-enhancement material.
A still further aspect of the invention relates to an integrated circuit structure including conductive transmission lines encapsulated in a transmission-enhancement material selected from the group consisting of high magnetic permeability materials (e.g., MgMn ferrites and/or MgMnAl ferrites) and high permittivity materials (e.g., barium strontium titanate, lead zirconium titanate, titanium oxide, tantalum oxide, etc.).
Other aspects, features and embodiments of the invention will be more fully apparent from the ensuing disclosure and appended claims.